This invention relates to systems and methods of phase detecting, including phase detectors, phase frequency detectors and methods of operating the same.
Phase detectors often are found in phase-locked loops, which may be used to generate clock signals in data communication systems, local area networks, microprocessors, and data storage applications (e.g., disk drives). A phase-locked loop typically includes a phase detector (or phase frequency detector), a charge pump, a low pass filter, a voltage-controlled oscillator (VCO), and a programmable divider. The frequency divider is located in the feedback path and tunes the VCO frequency (fVCO) to a multiple of the reference frequency (fREF). In one frequency synthesis approach, the frequency divider divides the VCO output signal frequency (fVCO) by N to produce a feedback signal with a frequency fVCO/N. The phase detector tunes the VCO until the phase of the feedback signal matches the phase of the reference signal. By changing the value of N, the output signal produced by the VCO may be changed in frequency steps that are equal to the reference frequency (i.e., fVCO=Nxc2x7fREF)
In this approach, the phase detector monitors the relative timing between the edges of the reference signal and the feedback signal and generates UP and DOWN output pulses depending on whether the transitions of the VCO output signal lead or lag the reference signal. The widths of these output pulses correspond with the times between the edges of the reference signal and the feedback signal. The UP and DOWN output pulses are applied to the input of the charge pump. The charge pump dynamically adjusts the charge supplied to the low pass filter. The resulting signal at the output of the low pass filter controls the frequency of the output signal generated by the VCO. Jitter (noise) generated by any of the components of the phase-locked loop, including the phase detector, directly produces jitter in the output VCO signal, reducing the performance of the frequency synthesizer.
The invention features improved systems and methods of phase detecting with high frequency and low jitter.
In one aspect, the invention features a phase detector comprising a latch having an input stage and an output stage. The input stage couples to the output stage through a dynamic storage node and includes a discharge circuit. The discharge circuit has a first input and a second input and defines a discharge path for discharging the dynamic storage node that is substantially symmetric with respect to the first and second inputs.
Embodiments may include one or more of the following features.
The discharge path preferably is substantially symmetric with respect to transitions to a state in which the first and second inputs both are high. The discharge circuit may include first and second anti-symmetric discharge subpaths. The first discharge subpath preferably comprises a base gate having an input coupled to the first discharge circuit input and an intermediate gate coupled between the base gate and the dynamic storage node and having an input coupled to the second discharge circuit input. The second discharge subpath preferably comprises a base gate having an input coupled to the second discharge circuit input and an intermediate gate coupled between the base gate and the dynamic storage node and having an input coupled to the first discharge circuit input. In one embodiment, the gates of the first and second discharge subpaths include metal-oxide-semiconductor (MOS) transistors (e.g., n-type MOS (NMOS) transistors).
The phase detector preferably includes a charge circuit for charging the dynamic storage node. The charge circuit may have a first input coupled to the second discharge circuit input and a second input. The charge circuit preferably is configured to charge the dynamic storage node when the first and second charge circuit inputs both are low. The charge circuit may include a base gate having an input coupled to the first charge circuit input and an intermediate gate coupled between the base gate and the dynamic storage node and having an input coupled to the second charge circuit input. In one embodiment, the base and intermediate charge circuit gates include p-type metal-oxide-semiconductor (PMOS) transistors.
The output stage preferably is configured to transition the second discharge circuit input to the logic level of the dynamic storage node. The output stage preferably is configured to transition the second discharge circuit input to a high logic level of the dynamic storage node in response to a rising edge of a signal applied to the second charge circuit input.
The first discharge circuit input preferably is coupled to an output of a second latch and the second input is coupled to an output of the output stage.
In another aspect, the invention features a discharge circuit having a first input and a second input and defining a discharge path for discharging the dynamic storage node that has substantially the same propagation delays between the first and second inputs and the dynamic storage node.
In another aspect, the invention features a phase detecting method. In accordance with this inventive method, the dynamic storage node is discharged with a characteristic discharge time in response to a transition of the first input from a low logic level to a high logic level when the second input is at a high logic level. The dynamic storage node also is discharged with substantially the same characteristic discharge time in response to a transition of the second input from a low logic level to a high logic level when the first input is at a high logic level.
As used herein, the term xe2x80x9chighxe2x80x9d refers to a high logic level. Similarly, the term xe2x80x9clowxe2x80x9d refers to a low logic level.
Among the advantages of the invention are the following.
The invention provides a phase detector system characterized by a low delay and a short pulse width. Because the inventive discharge circuit defines a substantially symmetric discharge path, systematic state transition mismatches are substantially avoided. This feature substantially reduces jitter produced at the output of the phase detector. As a result, the inventive phase detector has a highly symmetrical output that may be advantageously used to improve the jitter performance and reference frequency feed through of charge pump-based phase-locked loops.